One of the most critical parameters affecting silicon integrated circuit functionality and yield is the amount of stress that is developed within the silicon substrate during device processing. Stresses, exceeding the mechanical yield strength of silicon (Si), will form Si crystal defects (e.g., dislocations and stacking faults), adversely affecting device performance and yield. A prominent source of stress occurs during the isolation process of electrical devices. Shallow trench isolation (STI) is used for features designed a 0.5 .mu.m or less. This process includes
etching a "shallow" trench (i.e., 0.5 .mu.m or less), PA1 growing a thin oxide immediately after etch, PA1 filling the trench with a dielectric (i.e., deposited oxide), PA1 "densifying" the dielectric, either by oxidizing the dielectric or using a high-temperature anneal in an inert ambient, and PA1 planarization of the dielectric.
As device geometries continue to shrink in size, and since stress is inversely proportional to area, it is of paramount importance to minimize stress during isolation processes as much as possible.
A 256 megabyte (MB) dynamic random access memory (DRAM) chip uses a "deep" trench array (as the capacitors) and STI to isolate the various transistors within the capacitor array. It has been determined that limiting the amount of oxide grown in the substrate is necessary to eliminate Si crystal defects in the trench-capacitor array. The method currently employed to "block-out" oxygen (O.sub.2) in the Si substrate is the use of a thin (&lt;5 nm) silicon nitride (Si.sub.3 N.sub.4) film deposited by low-pressure chemical-vapor deposition (LPCVD) immediately after a thin oxide is grown in the STI. The thickness of the Si.sub.3 N.sub.4 film is specified as being 5 nm or less. The reason for this thickness limitation is that this film has been found to be etch-resistant in hot phosphoric acid baths (e.g., to remove pad Si.sub.3 N.sub.4) as well as in hydrofluoric acid baths (to remove thermally grown oxides). Thicker LPCVD-Si.sub.3 N.sub.4 films used as Si.sub.3 N.sub.4 liners in STI trenches have shown to etch readily in hot phosphoric acids.
One problem associated with the thin Si.sub.3 N.sub.4 liner has been its propensity to trap electrical charge. The charge-trapping behavior (interface and bulk) of the Si.sub.3 N.sub.4 liner has been observed to enhance STI-bounding leakage (N well to N well) in the sense amplifiers (i.e., "support circuitry") of the DRAMs, thus causing high standby currents. Recent data clearly shows that the Si.sub.3 N.sub.4 liner lowers the threshold voltages (Vt) and enhances junction leakage by several orders of magnitude.
To ascertain the amount of charge that is trapped by the Si.sub.3 N.sub.4 liner, blanket wafer experimental lots were processed consisting of (1) thermally-grown oxide (SiO.sub.2 -10 nm), (2) LPCVD-Si.sub.3 N.sub.4 (4 nm), and (3) 10 nm SiO.sub.2 /4 nm LPCVD-Si.sub.3 N.sub.4. Simple metal-insulator-semiconductor (MIS) structures were fabricated by depositing aluminum through a dot mask onto the insulating film(s). C-V measurements (low- and high-frequency) were conducted and result indicated that (1) the thin Si3N4 film alone contains approximately two orders of magnitude more charge-trapping states than the oxide (i.e., 10.sup.12 versus 10.sup.10), and (2) the combination of the oxide and Si.sub.3 N.sub.4 decreases the density of charge-trapping states only marginally (e.g., .about.5.times.10.sup.11 versus 10.sup.10). Ideally, it would be best to develop or deposit a thin Si.sub.3 N.sub.4 film that would not trap charge and still be resistant to hot phosphoric acid and hydrofluoric acid.